The present invention relates to a Fraction-N synthesizer, and more particularly, to a Fraction-N synthesizer with a sigma-delta modulator for variable reference frequencies.
In general, frequency synthesizers use a reference signal of a reference frequency as a source signal and synthesize a desired output signal having a frequency that is a multiple of the reference frequency. Please refer to FIG. 1. FIG. 1 shows a block diagram of a conventional Fractional-N frequency synthesizer 100. The frequency synthesizer 100 includes a phase detector 110, a loop filter 120, a voltage controlled oscillator (VCO) 130, a frequency divider 140, and a sigma-delta modulator (SDM) 150. The frequency divider 140 is utilized for dividing the output frequency Fout of an output signal Sout by a division factor (i.e. N±n) provided by the sigma-delta modulator 150, and for generating a feedback signal Sb. The phase detector 110 then compares phases of the feedback signal Sb and the reference signal Sref and outputs a phase difference signal Se representing the phase difference between the feedback signal Sb and the reference signal Sref. The phase difference signal Se is filtered by means of the loop filter 120 to generate a control voltage Vt for controlling the VCO 130 to generate the output signal Sout. The output frequency of the output signal Sout is a function of the control voltage Vt.
In the conventional Fractional-N frequency synthesizer 100, the division factor, which is utilized for dividing the output signal Sout, is switched between two or more integer values determined by the sigma-delta modulator 150. Please refer to FIG. 2. FIG. 2 shows a block diagram of the sigma-delta modulator 150 shown in FIG. 1. The sigma-delta modulator 150 includes an integral end source 151, a fractional end source 152, adders 156 and 158, a low-pass filter 154, a quantizer 155, and a base multiplier 157. Please note that, since the component of the conventional sigma-delta modulator 150 is considered well-known in the pertinent art further details are omitted for brevity. The integral end source 151, could be a memory register, provides the integral part N and the fractional end source 152, could be a memory register, provides the fractional part FE. The low-pass filter 154 can be configured as a multiple-order low-pass filter to filter the fractional part FE. The quantizer 155 quantizes the filtered fractional part FE into a specific quantization value that lies in a range +n to −n with multiple levels. The quantization value within a range from +n to −n is then multiplied by a fixed base value B utilized by the base multiplier 157. The negative feedback is implemented to feed the computation result of the base multiplier 157 to the adder 158, where the adder 158 subtracts the computation result of the base multiplier 157 from the fractional part FE. As shown in FIG. 2, the adder 156 combines the integral part N with each obtained quantization value in a range +n to −n to generate a sequence of dividers ranging from N−n to N+n. Therefore, the long-term average generated by the sigma-delta modulator 150 is equivalent to N+FE. The relationship between the average output frequency Fout of the output signal Sout and the reference frequency Fref of the reference signal Sref can be expressed as follows:Fout=Fref×(N+FE)  Formula (1)
The base value B provided by the base multiplier 157 can be decided by the reference frequency Fref and the required output frequency resolution Fres as follows:B=Fref/GCD(Fref,Fres)  Formula (2)
In Formula (2), GCD represents the Greatest Common Divisor. That is, GCD (Fref, Fres) is the greatest common divisor of Fref and Fres.
In the above scheme, the base value B is obtained from the reference frequency Fref. If the reference frequency Fref is changed, the base value B in the base multiplier 157 also needs to be changed to a specific value. That is, the sigma-delta modulator 150 in the conventional frequency synthesizer 100 is designed to support a single fixed reference frequency Fref. If there are requirements for variable reference frequencies, a corresponding base value needs to be calculated for each reference frequency and different feedback loop circuits may need to be designed for each reference frequency in the sigma-delta modulator 150, causing high space consumption and less efficiency. Therefore, how to design the sigma-delta modulator having a constant base value, regardless of the reference frequency in order to improve performance of the frequency synthesizer becomes an important issue in the manufacture of the frequency synthesizer.